EUP7998 ds7998 ver1.1 aug. 2010 1 sink/source ddr termination regulator description the EUP7998 is a high performance linear regulator designed to provide power for termination of a ddr memory bus. it significantly reduces parts count, board space and overall system cost over previous switching solutions. the EUP7998 maintains a fast transient response using only 20 f or 30 f output capacitance. the EUP7998 supports a remote sensing function and all power requirements for ddr, ddr2, ddr3 and low power ddr3/ddr4 vtt bus termination. the EUP7998 provides current and thermal limits to prevent damage to the linear regulator. additionally, the EUP7998 generates an open-drain pgood signal to monitor the output regulation. an active high enable pin en can pull vtt low, but refout will remain active. a power savings advantage can be obtained in this mode through lower quiescent current. the EUP7998 is available in the 3mm features z vldoin input voltage range: 1.1v to 3.5v z vin input voltage range: 2.375v to 5.5v z typically 3 f mlccs stable for ddr z fast load-transient response z 10ma buffered reference (refout) z meet ddr, ddr2 jedec specifications. supports ddr3 and low-power ddr3/ddr4 vtt applications z power-good window comparator z with soft start, uvlo and ocp z thermal shutdown z available in 10-pin 3mm 3mm tdfn and sop-8 (ep) packages z rohs compliant and 100% lead(pb)-free halogen-free applications z notebook/desktop/server z ddr memory termination z telecom/datacom, gsm base station, lcd-tv/pdp-tv, copier/printer, set-top box typical application circuit figure 1. for tdfn-10 package
EUP7998 ds7998 ver1.1 aug. 2010 2 typical application circuit (continued) figure 2. for sop-8(ep) package pin configurations package type pin configurations package type pin configurations tdfn-10 sop-8 (ep) pin description pin tdfn-10 sop-8 (ep) description refin 1 1 external reference input vldoin 2 2 power supply of the ldo. internally connected to the output source mosfet. vo 3 3 output of the ldo pgnd 4 9 (thermal pad) power ground vosns 5 4 voltage sense input for the ldo. connect to positive terminal of the output capacitor. refout 6 5 buffered reference output. the output of the unity-gain reference input buffer sources and sinks over 10ma. bypass refout to gnd with a 0.1 f ceramic capacitor. en 7 6 enable control input. active high input. for ddr vtt application, connect en to slp_s3. gnd 8 7 ground pgood 9 - open-drain power-good output vin 10 8 power supply input. connect to the system supply voltage. bypass vin to gnd with a 1 f or 4.7 f ceramic capacitor. note(1):pgnd, gnd and thermal pad must be connected together outside under thermal pad.
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